The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an integrated delay circuit instead of a plurality of delay circuits corresponding to respective banks in order to reduce its size.
A semiconductor memory device includes a bank for storing data, a peri region for controlling the bank and performing a read/write operation and a power circuit.
The bank is formed by partitioning a data storage region of the semiconductor memory device into a predetermined size for an efficient use of the data. A single chip may have a plurality of banks. The bank includes a cell for storing data allocated to its X and Y addresses and a controller with an X and Y decoders.
A typical semiconductor memory device includes various delay circuits for various purposes in order to control a lot of banks. It includes as many delay circuits for controlling the banks as the number of banks.
FIG. 1 is a schematic block diagram of a typical semiconductor memory device.
Referring to FIG. 1, the typical semiconductor memory device includes banks 111, 112, 113, 114, 115, 116, 117 and 118, a control circuit 100 for controlling the banks 111 through 117 and delay circuits 121, 122, 123, 124, 125, 126, 127 and 128 corresponding to the respective banks 111 through 117. The control circuit 100 includes a peri block, a power circuit and other circuits for controlling operation of the bank. The delay circuits 121 through 128 adjust timings of operations of the banks 111 through 118.
Hereinafter, operations of the delay circuits 121 through 128 corresponding to the respective banks 111 through 118 in a refresh mode will be described for example.
As is well known, the semiconductor memory device may perform auto/self refresh operations, and the refresh operation includes an active operation and a precharge operation. A precharge reference signal for the precharge operation of each of the banks 111 through 118 is not generated by the control circuit 100 whereas an active reference signal for the active operation is generated by the control circuit 100 in response to an external command and the like. Instead, each bank generates its precharge reference signal by delaying its active reference signal by a predetermined time interval. For this, the semiconductor memory device includes a plurality of delay circuits 121 through 128 corresponding to the respective banks 111 through 118.
The semiconductor memory device may include a lot of delay circuits adjusting timings of various operations of the respective banks 111 through 118. As the memory capacity increases and the number of banks increases, the number of delay circuits also needs to be increased, which is becoming a burden on chip size of the semiconductor memory device.
A delay circuit, such as an RC delay circuit, which needs a great area further increases such a burden.